The present invention relates to a semiconductor integrated circuit such as a data processor having a memory interface controller coupled to a double data rate (DDR) type synchronous memory, e.g., a DDR-SDRAM (Synchronous Dynamic Random Access Memory), and particularly to a technology for synchronizing read data sent from a synchronous memory to an internal clock on the memory interface controller side.
A microcomputer to which a memory interface controller enabling a DDR-SDRAM to be directly connected thereto is on-chipped, has been described in a patent document 1 (Japanese Unexamined Patent Publication No. 2001-14213). This is one in which the memory interface controller for controlling the DDR-SDRAM is provided inside a processor to control the DDR-SDRAM through the use of an operation clock frequency of the microcomputer. Synchronizing a clock signal for the DDR-SDRAM to an internal clock on the memory interface controller side has not yet discussed in detail.